CPLD
美 
英
- 网络复杂可编程逻辑器件(Complex Programmable Logic Device)；复杂的可编程逻辑器件；可编程器件
例句
No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board.
最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。
An interpolation algorithm fully making use of the characteristic of CPLD high frequency is designed used for the grating torque sensor.
针对设计出的光栅转矩传感器，利用CPLD工作频率高的特点，采用高频脉冲插值法进行精确计数。
Micro-controller is the bond between the two parts, it acts as the USB controller in one way, and communicates with CPLD in the other.
微处理器是两个部分之间连接的纽带，一方面作为USB控制器，另一方面要和CPLD通信。
The realization method of the changeable address generator in CPLD and its source routine written in H-ABLE language were provided.
给出了在CPLD中实现可变地址发生器的设计方法和用H-ABLE语言编写的源程序。
In this paper, a radar intelligence fiber transmission system is implemented by using CPLD, and its simulation waveforms are also given.
采用可编程逻辑器件，实现了一种可传输雷达情报信息的光纤传输系统，并给出了仿真波形。
The time driving signals of CIS and the handclasp signals of the system are both designed by CPLD.
CIS的时序信号以及系统的握手信号均由CPLD完成设计。
This interface handles the sensing, linking, and communication of the microchip and also controls multiple servo motors by CPLD.
由单晶片来完成感测、通讯、连结以及互动的工作，由CPLD完成多轴伺服机的控制。
As peripheral circuit logic control module, CPLD realizes the flexible reliable control of the periphery circuit.
CPLD作为逻辑控制模块，实现了对外围电路的灵活可靠控制；
This article mainly analyzed CPLD time order control, data acquisition, data conversion. Chip selection and hardware circuit were given.
重点分析了CPLD测频时序控制模块、数据采集模块、数据处理模块，给出了芯片选型和硬件电路设计。
The peripheral devices of CPU could be simplified. As dead-time was actualized, the short through of phase bridge could be avoided.
CPLD可简化控制芯片的外围设置，同时能实现开关管的死区控制，避免了相桥臂直通。
CPLD using the top of the control procedures and the underlying graphics input VHDL mixed language design of the modular design method.
CPLD的控制程序采用顶层图形输入法和底层VHDL语言模块设计的混合设计方法完成。
This dissertation uses a CPLD device to design drive circuit for the linear array CCD, which fully meet its drive requirements.
本文使用CPLD器件设计了一种适用于线阵CCD的驱动电路，完全满足其驱动要求。
That system is measured by the network of CPLD phase measure, SCM and display module three fractions constitutes.
系统由CPLD相位频率测量模块、单片机和显示模块三个部分组成。
A large number of logic circuits are designed by CPLD programming, then the interface circuit is simplified.
通过对CPLD编程完成大量的逻辑电路设计，简化了接口电路。
Take charge the rigging out and testing of a metrical equipment. Use CPLD to finish control and measurement.
负责某小型测试设备的研制、装配、调试、实验，并参与系统性联调试验，使用CPLD控制。
DSP+CPLD mode make this system rather programmable, and system's operation state could be changed easily.
DSP+CPLD模式使得本系统具有强大的可编程性，能非常方便的改变系统的工作状态。
CPLD after the initialization may be independent to DSP carries on the trigger pulse signal the formation.
CPLD在初始化后，可以独立于DSP进行触发脉冲信号的形成。
The invention also discloses a device for sintering firmware connected with an E2PROM on a CPLD.
本发明同时公开了一种CPLD上连接有E2PROM设备的固件烧结装置。
CPLD manages chip logic of the keyboard electric circuit, and DM642 external interrupt monitors states of the button.
CPLD管理键盘电路中的芯片逻辑，DM642的外部中断监控按键的状态。
The design of digital control system includes DSP interrupt service routine and CPLD logic control.
数字控制系统软件设计，包括DSP中断服务子程序和CPLD逻辑控制。
The single chip computer controls frequency and phase of ultrasonic motor by controlling CPLD.
用单片机控制CPLD的两个输入口，从而达到改变超声波电动机输入频率和相位的目的。
All conversion circuits and control signals that other modules require are produced by CPLD.
CPLD用来生成系统各模块所需的译码电路和控制信号。
The CPLD Application in the Remote and Multichannel Data Acquisition System .
CPLD在远程多路数据采集系统中的应用。
The chapter 3 expatiate the EDA, the hardware description language, the programmable device and the suppliers including CPLD and FPGA.
第三章详细介绍了EDA技术、硬件描述语言的相关概念，以及可编程器件的原理和厂商情况，包括CPLD和FPGA等。
CPLD+DSP structure is used to design control system and their control tasks are reasonably arranged.
控制系统设计采用CPLD+DSP的架构，对各自承担的控制任务进行了合理分配。
In view of the system's complexity, high-speed demands, the hardware platform based on DSP and CPLD is designed.
论文针对系统复杂性、高速性的需求，设计了基于DSP和CPLD的硬件平台总体结构。
Use CPLD to control the CMOS image sensor and the flash storage memory to record the image in the image record part.
其中图像摄取部分采用CPLD控制CMOS图像传感器采集图像，并把图像数据存入大容量闪速存储器。
Generate the VME file required for updating Lattice CPLD in embedded systems.
软件升级时所需的VME文件生成所需源代码。
CPLD: Complex Programmable Logic Device .
复杂可编程逻辑器件
The CPLD module has been developed to implement system logic control and sampled data storage by VHDL.
采用硬件描述语言（VHDL）对CPLD进行开发，实现了系统的逻辑控制和采样数据的存储。
Visiting conflict that MCU and CPLD visit the same RAM in same time can be avoided by applying interruption and software timing strategy.
单片机与CPLD共用外部RAM，采用中断和软件定时策略解决了访问冲突问题。
DSP is the core of the hardware platform; CPLD is used to coordinate and control.
该硬件平台以DSP为处理核心，CPLD用来完成控制协调。
After estimation of PRI, the PRI tracker(also called wheel tracker) is designed based on Complex Programmable Logic Device(CPLD).
在PRI参数估计之后，设计了基于可编程逻辑器件（CPLD）的PRI跟踪器（或称为飞轮跟踪器）。
This paper provides a scheme of EPP parallel interface controlled by CPLD.
详细介绍了一种在CPLD控制下实现的微型机EPP并行接口设计方案。
A hardware development platform for the computer numerical control system was built based on the DSP+CPLD.
针对柔性化制造要求，构建了以DSP+CPLD为基础的数控系统平台。
A new method of digital phase locked loop based on digital signal processing(DSP) and complex programmable logic device(CPLD) was proposed.
提出了一种基于数字信号处理技术（DSP）和可编程逻辑控制器件（CPLD）的全数字锁相方法。
The adjustments of current pulse width and frequency are achieved by using SMC and CPLD.
采用单片机与可编程逻辑器件实现电流脉冲宽度脉冲频率的调节；
The kernel framework of the controller is DSP+CPLD.
该控制器采用的是DSP+CPLD的核心架构。
With MCU and CPLD, a telephone calling system is designed in the paper.
以单片机与CPLD为核心，设计了电话呼叫系统。
The CPLD realized the auto data acquisition under the control of the chip.
在单片机控制下，由CPLD自动实现荧光光谱数据的高速采集。
