FPGA
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英
- 网络现场可编程门阵列(Field Programmable Gate Array)；现场可编程闸阵列；可编程逻辑器件
例句
Hence, FPGA fault tolerant design technology must be developed to make up for the insufficiency in radiation resistance of its components.
在面向航天应用的FPGA设计中，必须采用容错设计技术来弥补器件本身抗辐射能力的不足。
Selecting team members with a strong interest in learning FPGA technology should be a primary objective.
选择对学习FPGA技术有浓厚兴趣的团队成员应该是首要目标。
Today, FPGAs are often the heart of the system , being designed into mainstream as well as state-of the-art high-volume products.
今天，FPGA往往是系统的核心。它不仅生产量大、技术先进，而且还进入了半导体产品的主流。
Gathering an ideal team is often a challenge for smaller design groups and organizations with limited FPGA design experience.
对于缺乏FPGA设计经验的较小的设计机构和组织来说，组建一支理想的团队经常是个挑战。
Occasionally it may be necessary to go back ten or more versions of the FPGA design to revisit a specific problem or subsequent fix.
偶尔会有必要回退十个甚至以上的FPGA设计版本来再现某个具体问题及随后相应的解决方法。
The design has been used in the data transmission of CMOS image sensor and has passed the FPGA prototype verification correctly.
目前本设计已应用到光电器件CMOS图象传感器的数据传输并通过了FPGA原型验证。
The design concept of a radar deceptive jamming modulator is presented, and its implementation structure based on FPGA is put forward.
提出了一种雷达欺骗干扰信号调制器的设计方案，给出了其在可编程门阵列（FPGA）中的实现结构。
The performance of an FPGA is dependent on its architecture including the design of its logic block and its interconnection fabric.
性能的FPGA实现取决于其结构的设计，包括其逻辑块和互连结构。
Extensive testing was required to both ensure that the VHDL models behaved properly and to ensure that the FPGA did not damage the NES.
需要做更多的测试，确保VHDL模块的行为正确，并确保FPGA没有损坏任天堂系统。
The core can be instantiated in the HDL capture of the FPGA design between the native waveform logic and the system bus.
核心可以用HDL来具化，HDL实现了本地波形逻辑和系统总线之间的FPGA设计。
It has some outstanding advantages, such as high scale integration, no need of peripheral circuit and being easy to use.
该系统可有效利用FPGA片内硬件资源，无需外围电路，高度集成且操作简单。
By modeling, designing in VHDL, and down-loading the designed programs into a FPGA hardware.
系统基带电路通过VHDL建模与设计，并在高速FPGA芯片中实现。
When generating an internal ROM in an Altera FPGA, the memory contents can be specified in a Memory Initialization File (. mif).
当在AlteraFPGA中产生一个内部ROM时，记忆体内容能够在记忆体初始化档（.mif）中得到说明。
DDC method based on FPGA is put up in this paper, which is realized with a high speed and a high performance.
提出了一种数字下变频的FPGA实现方案，实现了高速、高性能的数字下变频。
Analysis of the traditional platform for electronic image stabilization defects, research and design of a dedicated FPGA-based platform.
分析了传统电子稳像平台的缺陷，研究并设计了基于FPGA的专用平台。
The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency, i. e.
接收器FPGA的信号，它准备好去接受一个方波产生在时钟频率的一半，即。62.5赫兹。
With a core processor of DSP, the system performs high-speed data collection through FPGA and MCU, and responds in real-time.
该系统以DSP为核心运算单元。利用FPGA和MCU进行高速数据采集。具有较好的实时性。
The use of Altera Corporation FPGA chips, the design of a car taillight controller, to achieve a state of auto taillights display control.
利用Altera公司FPGA芯片，设计一个汽车尾灯控制器，实现对汽车尾灯显示状态的控制。
FPGA-based implementation of LMS algorithm is one of the key techniques in the application of adaptive array antennas.
LMS算法的FPGA实现是自适应天线阵用于实践的关键之一。
This put the printed circuits or printed wiring in the finished plate called a printed wiring board, also known as printed boards or fpga.
这样就把印制电路或印制线路的成品板称为印制线路板，亦称为印制板或印制电路板。
This paper applies the motion compensation-based algorithm to deinterlacing system and deeply researches the FPGA design of the system.
本文采用基于运动补偿的算法，对去隔行系统及其FPGA设计作了深入的研究。
Enough bypass capacitors should be placed close to the power and ground pins of FPGA. Use capacitors with good high frequency response.
FPGA的电源和接地引脚附近应该放置足够多的旁路电容器。使用优质高频响应电容器。
FPGA got rapid development since its birth; it has become one of the most popular implementation media for digital circuit.
现场可编程门阵列（FPGA）自诞生以来得到了迅猛的发展，已经成为数字电路最常用的实现载体。
The total design plan of the system is shown based on the design request. The PID controller based on FPGA is designed.
并根据设计要求，采用再生制动实现了电机制动控制，给出了控制器的整体设计方案。
Contrast to the DSPs , FPGAs has more hardware resources, and can be used to deal with faster and better flexibility.
较DSP而言，FPGA具有更多的硬件资源可以利用，处理速度更快，灵活性更好。
This algorithm had been implemented in ALTERA's FPGA, and could be applied to other networks.
该算法已经在Altera公司的FPGA上实现，而且可以推广到其他网络。
Algorithm and its FPGA implement computer simulation confirm the effectiveness of this structure.
计算机仿真和FPGA硬件仿真验证了该结构的可行性。
This paper proposes a new fault detection method of interconnect resource in(FPGA) from the point of view of application.
从面向应用的角度出发，针对FPGA内部互连资源提出一种新的故障检测方法。
For adopting high-powered DSP processor and FPGA chip, the system have powerful operation ability and powerful peripheral managing ability.
采用高性能DSP和FPGA构成核心处理模块，使系统在具有强大运算能力的同时又具有强大的外设管理能力；
However, with acceleration and deceleration control process as a whole, quite independently from FPGA internal electronic gear.
但是，整个加减速随动控制过程，则完全是由FPGA内部的电子齿轮独立完成的。
DSP and FPGA technologies are used for cell and channel coding, which improves the error-resilient performance.
利用DSP和FPGA技术进行信元和信道编码，提高了系统的抗误码性能；
The amplitude-phase imbalance of a multi-channel radar receiver was corrected on an FPGA.
在FPGA上对多通道雷达接收机幅相不一致进行了校正。
Originally, the plan was to prototype the entire system using FPGAs , then migrate to ASICs once initial production turned to volume.
起初，打算使用FPGA作出整个系统的样机；一旦试生产转为量产，然后就转向设计ASIC。
Under a license agreement with Actel Corp. , the company will manufacture FPGAs that were discontinued in 2006.
根据与Actel公司达成的一项许可协议，BAE系统公司将继续生产已经于2006年停产的FPGA。
Hardware implementation includes FPGA and its peripheral circuits and microprocessor and its peripheral circuit design.
硬件实现主要包括FPGA及其外围电路和单片机及其外围电路的设计。
The main work of this thesis is to design a FPGA-based adaptive filter implemented by pure hardware.
本文的主要工作是设计基于FPGA的纯硬件实现的自适应滤波器。
The usual method is to include a tiny program inside a piece of block RAM (BRAM) within the FPGA bitstream.
通常的方法是在FPGA比特流中的一段块RAM（BRAM）内包含一个小程序。
The result of fixed-point simulation also provide the design basis for the FPGA implementation.
最终的定点仿真结果也为该算法的硬件实现提供了很好的设计依据。
This article proposed the technology of estimation common-mode noise with the energy of switching cycle and FPGA as the main component.
本文提出了用FPGA作为主要器件、以能量为指标的共模噪声评估技术。
In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance.
在多FPGA设计中，时钟信号的传输延时造成了FPGA间的大时钟偏差，进而制约系统性能。
