pll
美 
英
- n.锁相环路；多聚L-赖氨酸
- 网络锁相环(phase-locked loop)；锁相回路；锁相环电路
英汉解释
例句
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
锁相环在微处理器领域中的一个重要应用就是为系统提供片内时钟，它是微处理器时钟电路中的核心模块。
Because of the better spur control than DDS, the Phase Locked Loop (PLL) frequency synthesis is usually used in frequency agile synthesis.
锁相频率合成（PLL）具有比DDS更优秀的杂散抑制能力，常用于捷变频率合成。
Compared with the structure of the commonly used PLL circuit, that of the circuit implemented by this way is simpler and easier to be made.
用该方法实现的电路，比通常所用的锁相环电路结构简单，而且易于实现。
If the frequency offset is large enough, the traditional PLL cannot be locked. Such situation would lead to the system corruption.
当频差较大时，接收端用于载波恢复的锁相环路无法锁定，导致系统不能正常工作。
The PLL includes a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider .
该PLL电路由一个鉴频鉴相器电路、一个电荷泵、一个低通滤波器、一个压控振荡器和分频器组成。
Therefore, a more thorough analysis of the output jitter, taking into account optimal loop bandwidth selection, is provided in this paper.
因此，本文在考虑最优带宽选择的情况下，对PLL输出时钟抖动特性进行了更深入的研究。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy.
采用了硬件锁相环技术，可更加有效实现同步采样，提高了采样精度。
USPIO-PLL, as an intracellular contrast agent, can label endothelial progenitor cells with high efficiency.
利用USPIO-PLL作为细胞内造影剂可以高效标记内皮祖细胞。
The second local frequency signal is provided by an integer-divider after PLL output.
二次变频的本振信号由PLL的输出信号经整数分频得到。
When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.
当水平的同步和振动者频率之间的巧合被发现的时候，搜寻模态被正常PLL操作代替。
A switched varactor array is proposed to suppress tuning gain fluctuation for the performance of the phase locked loop (PLL).
该振荡器包含了一个开关可变电容阵列，用以抑制调谐增益的变化。
A fast locking phase-locked loops (PLL) with a dual-slope phase frequency detector circuit is presented.
文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计。
Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro-machined gyroscope are designed.
结合锁相环的特性，设计一种电容式微机械陀螺双环路自激驱动电路。
The technology of PLL has always been the research emphasis in the field of measurement and control of power system.
锁相同步技术一直都是电力系统测控领域的研究重点。
DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.
PLL混合频率合成技术能综合两者的优点，已成为现今频率合成领域的重要研究方向。
The design of PLL, AGC, IQ and impedance mATched parts are analyzed. The implement of the circuit and the test result are provided.
对PLL、AGC、IQ调制以及阻抗匹配等各部分设计进行了分析，给出了具体的电路实现和测试结果。
The signal processing circuses , including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed.
分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。
A detailed discussion about the hardware design including PLL, DLL of the GPS signal acquisition and tracking is focused on.
最后详细讨论了GPS信号接收机硬件的设计，包括捕获跟踪、PLL、DLL的设计。
of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks.
相位频率检测器（PFD）和修改其他的PLL模块。
A novel detection method of power quality disturbance based on an improved phase-located loop (PLL) system is brought forward in this paper.
提出了一种基于改进锁相环（PLL）系统的电能质量扰动检测方法。
But if the Doppler frequency offset exceed the capture range of PLL, the carrier synchronization will fail.
但是，一旦多普勒频移超出了锁相环的频率捕捉范围，就无法完成载频同步。
The core instrument for frequency-following is the PLL. The DSP is used to realize the regulating of the dead time on-line.
用锁相环作为频率跟踪的核心器件，根据最佳死区的理论，用DSP实现死区的在线调节。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一种面向系统数学模型的模块连接式锁相环路计算机辅助分析方法。
Changes in the minimum pulse width can adversely effect a PLL's static phase offset and performance characteristics.
最小脉冲宽度的变化可能不利地影响PLL的静态相位偏移和性能特征。
PLL is used for generating carry synchronization signal.
采用平方环实现载波同步信号的提取。
The PLL can provide a very wide frequency range as the input clock is fixed.
在输入时钟固定的情况下，锁相环能够输出非常宽的频率范围。
PLLs have many applications in integrated circuits ranging from agile frequency synthesis and clock recovery circuits.
锁相环（Phase-lockedloop，PLL）广泛应用于频率综合器、时钟恢复电路等集成电路中。
AD1896 (Analog Devices) - selected for its low spurious tones, low distortion, and exceptionally low PLL corner frequency.
AD1896-（类比装置）为它的低点膺造的明暗，低的扭曲和例外地低的PLL角落频率选择。
The automatic tuning system in a PLL technique is simply introduced.
文中简单介绍了锁相环自动调谐系统。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
为满足高速和精确的采样，论文在控制器硬件中设计了锁相环电路。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
前者在常规的采用电压外环、电流内环的双闭环控制基础上，搭建数字锁相环、数字滤波器。
A high-order phase-locked loop(PLL) for radio frequency synchronization is designed.
文章介绍一种用于射频同步的高阶环设计方法。
Operation theory and realization method of stator-flux-angle in engineering based on digital phase-locked-loop (PLL) are presented.
就定子磁通角工程上的实现方法，提出了数字锁相环法，分析了其工作原理和实现方法。
At signal tracking aspect, first, the elements of code loop and carrier loop was proposed based on the basic phase-locked loop (PLL).
跟踪方面，以基本锁相环为理论基础，分析并确定了码跟踪环和载波跟踪环的环路参数；
The tune measurement systems in the BEPC storage ring by using PLL are introduced in this paper.
介绍了采用锁相法的BEPC储存环自由振荡频率测量系统。
for keeping the frequency and phase synchronous to the grid , a pll ( phase locked loop ) is necessary.
为了使并网电流和电网电压同频、同相，需要使用锁相环技术。
PLL is a close loop control system, it is used to high precision frequency and phasic control.
锁相环路是一个闭环控制系统，用于高精度的频率和相位控制。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
针对汽车音响收音数字调谐系统的实例，介绍一种广播用双波段锁相环频率合成电路的设计方法。
How will it be happened when IO port is set to output and internal PLL HIGH?
当Port7设定成输出且启动内部上拉电阻时，会发生什么情形？
